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Si5040
LOL=1?
Y
VCOCAL[1:0] = 01?
VCOCAL[1:0] = 00?
VCOCAL[1:0] = 10
(Default)?
VCOCAL[1:0] = 11?
Y
Is refClk
present?
Y
Y
The internal VCO pull
range will be automatically
re-centered to the
reference clock frequency
Y
Y
Is refClk present?
Y
to start the CDR lock
N
acquisition process.
N
The entire VCO
frequency range will be
swiped to start the CDR
VCO stays at the center
of its frequency range
awaiting for refClk
Invalid mode!
LOL will stay on.
lock acquisition process.
Figure 14. Receive and Transmit CDR and VCO Behaviors Upon Declaring LOL
5.5. Receiver Slice Control
In order to optimize the bit error rate performance of the system, the receiver supports automatic and manual
adjustment of the 0/1 decision threshold (slice control). Four slice modes can be programmed via Register 20 as
detailed below:
?
?
?
?
AutoSlice Mode (sliceEn[2:0] = 001): The slice is automatically set without any control by the user. An internal
estimate of the eye opening is used to automatically adjust the slice voltage. This mode can be used when there
is no FEC processor as it continually adjusts the slice voltage. Registers 22/21 have no effect on this mode of
operation.
Constant Duty Cycle Mode (sliceEn[2:0] = 010):
This mode continually adjusts the slice voltage to maintain a user-selected duty cycle at the limiting amplifier
output. The duty cycle can be set in the sliceLVL register (Registers 22 and 21). This mode can be used when
there is no FEC processor, however, if the duty cycle is dynamically controlled the recommended duty cycle
step size is less than or equal to 0.1%. In an actual system the duty cycle should not be set to less than 45% or
greater than 55%. For the case of maximum dispersion, an optimally-set duty cycle will typically perform slightly
better than Autoslice.
Proportional Mode (sliceEn[2:0] = 011):The slice offset is defined as a percentage of the peak-to-peak value of
the input signal. The percent value is written in the sliceLVL register (Registers 22 and 21) as an offset from
50%. Due to drifts and temperature variations in the silicon, the slice offset values must be dynamically modified
at a rate of 100 ms or faster. This mode is recommended only when a FEC processor is present to control the
slice level.
Absolute Mode (sliceEn[2:0] = 100): The slice offset is defined as an absolute voltage. The offset can be set in
the range of –240 to +240 mV in the sliceLVL register (Registers 22 and 21). Just as in proportional mode, the
slice offset values must be dynamically modified at a rate of 100ms or faster. This mode is recommended only
when a FEC processor is present to control the slice level.
Autoslice and constant duty cycle are the preferred slice modes of operation for Telecom and Datacom
applications.
Rev. 1.3
23
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